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Features
* * * * * * * * * * * * * * *
Single-chip WiMax Transceiver @ 3.5GHz Fully Differential Design Low-IF Receiver Architecture; Requires No External Filters Self Calibration Mode for RX / TX Filters Supports Channel Bandwidths of 1.75, 3.5, and 7MHz Modulation up to 64QAM Ultra-fast Fractional-N Synthesizer Sensitivity < -68dBm @ 64-QAM, CR=3/4, 7MHz BW Phase Noise Synthesizer: 0.8 (-37dBc) Low Supply Voltage: 2.7V TX Output PRF: -12 dBm RX/TX Operating Current: 200/320mA Typical Low Power Off Current: < 20A Typical 56-lead QFN Package Low External Component Count of only a few Passives
WiMax Transceiver 802.16-2004 AT86RF535A
Applications
* 3.5 GHz Band Wireless Communication Devices * IEEE(R) 802.16-2004 Radios * Supports OFDM up to 64QAM
Preliminary
Figure 1.
AT86RF535A Block Diagram
TX Power Control
RX Gain Control
LNA
I Q
Synthesizer
Driver
I Q
Config Register
CLK
5108B-WiMax-2/06
Description
Atmel's AT86RF535A is a fully integrated, low cost RF 3.5GHz Low-IF conversion transceiver for WiMax applications. It combines excellent RF performance with low current consumption at the smallest die size. The AT86RF535A chip is fabricated on the advanced AT46000 SiGe BiCMOS process. The transceiver combines LNA, PA driver, RX/TX mixer, RX/TX filters, VCO, Synthesizer, RX Gain control, and TX Power control, all fully digital controlled. The number of external components is limited to only a few devices.
Quick Reference Data
Table 1.
Symbol FRF DFRS VDD IDDRX IDDTX IDDPOFF SENS PRF PN TAMB Note:
Quick Reference Data
Parameter Input Center Frequency Frequency Resolution Supply Voltage Supply Current Supply Current Supply Current Sensitivity QPSK Sensitivity 64QAM TX Output Power Integrated Phase Noise of Synthesizer Operating Ambient Temperature Applied to VDD pins Receive mode Transmit mode, -5 dBm includes Balun Power-off mode, only in "External CLK oscillator" mode BW=1.75MHz, CR=1/2, S/N=9.4dB BW=7MHz, CR=3/4, S/N=24.4dB FRF= 3.5 GHz, 15dB back off for 64QAM, EVM=-34dB, includes Balun Integrated over Frequency Range 50kHz ...1MHz -30 -12 0.8 27 +70 3.0 3.3 200 320 20 -89 -68 Conditions Min 3.4 Typ 3.55 Max 3.7 39.2 3.6 Unit GHz Hz V mA mA A dBm dBm deg rms C
All voltages are referenced to GND. VDD=3.0V TAMB=27C, unless otherwise noted.
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AT86RF535A [Preliminary]
Electrical Characteristics
Table 2.
Symbol System FRF ZIN SENS PIN,MAX NFSSB GRX,STEP GRX,RANGE tRX/TX LLO-ANT ACR1 ACR2 Input Center Frequency Differential Impedance at LNA Input Sensitivity QPSK 1/2 Sensitivity 64QAM 3/4 Maximum Input Power Noise Figure Single Side Band RX Chain: Gain Steps RX Chain: Gain Range RX to TX Switching Time LO Leakage to Antenna Adjacent Ch. Rejection Nonadjacent Ch. Rejection All gain modes, includes Balun 16QAM 3/4 64QAM 3/4 16QAM 3/4 64QAM 3/4 Includes a matching inductor and two series capacitors BW=1.75MHz, S/N=9.4dB BW=7MHz, S/N=24.4dB BW=7MHz, EVM=24.4dB High gain mode, includes Balun w/o Frontend loss -20 4 0.76 95.5 5 tbd -11 -4 -30 -23 5 3.4 3.55 50 -90 -69 3.7 GHz diff. dBm dBm dB dB dB s dBm dB dB
Receiver Characteristics(1)
Parameter Conditions Min Typ Max Unit
Baseband filters, DC cancellation, RSSI, IQ outputs ROUT COUT VOMAX VOUT GB,OFFSTEP GB,RANGE Output load resistance Output load capacitance Maximum Output Voltage Nominal I or Q output Voltage I, Q output buffer: Gain Offset Steps I, Q output buffer: Gain Range Low-IF Center Frequency: 1MHz 2MHz 4MHz Note 2 Note 3 Note 2 0.9 -9 1.75 3.5 7 -42 1.0 2.0 4.0 1.0 1.1 -36 Pin to GND Pin to GND Differential Differential at the load specified Output buffer gain offset = 0dB Backoff -15dB relative to I or Q 1 0.141 0.76 +2.25 1 10 M pF V Vrms dB dB
BW3dB
3-dB Bandwidth of Filter
MHz
IMRR FIF CMD Note:
Image Rejection Ratio Low-IF Frequency Common Mode IQ Voltage
dB MHz V DC
1. VDD=3.0V, TAMB=27C, FRF=3.55 GHz, specific application circuit TBD, unless otherwise noted 2. Internally adjusted by built-in self test 3. Calibration vector access able over SPI Register
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Table 3.
Symbol System FRF ZOUT POUT tTX/RX GPA,RANGE GLSB,STEP
Transmitter Characteristics(1)
Parameter Conditions Min Typ Max Unit
Output Center Frequency Differential Impedance at Driver Output TX Output Power TX to RX Switching Time TX Chain Gain Control Range TX Chain Gain Control LSB Step Size Low-IF Center Frequency: 1MHz 2MHz 4MHz Note 2 Note 3 64QAM 3/4 Differential Peak, Differential For 64QAM modulated signals
3.4
3.55 50 -12
3.7
GHz diff dBm
tbd 50 71.9 0.76 1.75 3.5 7 -43 -34 10 1 1.05
s dB dB
BW3dB
3-dB Bandwidth of Filter
MHz
LCarr EVM ZIN VIN VIN, DC Note:
Carrier Leakage Error Vector Magnitude IQ Input Impedance IQ Input Voltage DC Input Voltage
dBc dB k diff Vp,diff V
1. VDD=3.0V, TAMB=27C, FRF=3.55 GHz, specific application circuit TBD, unless otherwise noted 2. Internally adjusted by built-in self test 3. Calibration vector access able over SPI Register.
Functional Description
The AT86RF535A is a fully integrated, low-cost Low-IF conversion transceiver for WiMax applications and is based on the IEEE 802.16-2004 standard. This product will provide transmit, receive, and frequency synthesis functions OFDM modulation schemes, as defined in the above specifications. It combines excellent RF performance at low current consumption. The transceiver combines LNA, PA driver, RX/TX mixer, RX/TX filters, VCO, Synthesizer, RX gain control, and TX power control, all fully digital controlled. The number of external components is limited to only a few devices. The AT86RF535A consists of a frequency-agile RF transceiver intended for use in 3.5-GHz licensed bands at data rates up to 26Mbps. Configuration and control registers and a bi-directional data communications interface to existing baseband devices from different vendors will be included. The AT86RF535A addresses the requirements of base station (BS) as well as subscriber station (SS) equipment. The device will operate down to 3.0V. The AT86RF535A is fabricated in Atmel's AT46000 advanced SiGe BiCMOS process technology and is assembled in a 8mm x 8mm 56-lead QFN package.
RX Path
The differential low noise amplifier (DLNA) makes use of a differential bipolar stage with resistive emitter linearization. For digital gain control operation, the DLNA supports the four gain modes
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AT86RF535A [Preliminary]
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AT86RF535A [Preliminary]
0, 6, 12, and 18dB. The linearity improves as the gain is reduced. The differential inphase quadraturephase mixer (IQMIX) utilizes a differential bipolar stage with emitter degeneration for the best linearity performance. A complex driving LO source was chosen for optimal LO leakage cancellation. The IQMIX has 4, 10, 16, and 22dB switchable gain. The receive poly phase filter (RXPPF) is designed as a frequency shifted leapfrog structure. The filter provides three different bandwidths at three different center frequencies. The bandwidth of this filter is tuned by built-in self test (BIST). The tuning process adjusts the cap values within the filter after power-up. The tuning can be determined via SPI. Image rejection is calibrated via SPI. Three digital controlled gain amplifiers (DGA1-3) are used to make necessary amplification available. Each stage supports the four gain modes 0, 6, 12, and 18dB. An additional fine gain stage DGB enables gain tuning of approximately 6dB in 0.76 dB steps. An output buffer gain offset matches the voltage swing to the respective BB input stage. The gain control is completely digital and affects LNA, MIX, and the three DGAs by using the same granularity for each stage. The BB/MAC provides the gain vector at a separate serial interface. A fast TX/RX switching is possible via TX/RX switch input pins controlled by the BB/MAC. The Low-IF conversion receiver does not have to amplify DC signals. But the gain setting produces different offsets in gain stages related to the output. To prevent signal saturation effects contribution, an offset correction takes place after each gain step. For dynamic range reasons, every stage has its individual offset correction stage. The DC feedback (DCFB) works as output offset compensation network which depends on actual gain setting. The internal gain control operation is optimized for fixed target amplitude. To adapt to different application requirements, the IQ output buffer DGB has a programmable gain offset from -1.5dB to 6dB in increments of 0.76dB. So, the nominal output voltage can be set between 180mVp and 650mVp. The gain is controllable via the register. The IQOB is able to drive a capacitive load on all four-output ports (RXI1, RXI2, RXQ1, RXQ2). The external pin CMD is an output pin, which delivers the common mode output voltage of the DGB.
TX Path
The transmit low pass filter (TXLP) filter is band limited concerning emission regulation and OFDM signals. So the input signal at the four-input ports (TXI1, TXI2, TXQ1, TXQ2) driving the TXLP could be a digital one but with defined levels. The complex filtered BB signal is upconverted with IQ Low-IF Upconverter IQUC. A complex driving LO source is chosen for optimal LO leakage cancellation. The output currents of the two mixer stages are added together. The resulting signal drives the power amplifier control (PAC) block. PAC is a Gilbert cell based current domain amplifier. Gain is controlled by DC voltage across the mixer core. In that way linear to dB gain control is achieved. The BB/MAC provides the gain setting vector at a separate serial interface.
Synthesizer
Voltage controlled oscillator (VCO) works at doubled LO frequency. This enables building complex LO phases for IQMIX and IQUC easily by using a divide by two and reduces load-pulling effects regarding DC current swing of the integrated PA. The VCO utilizes a differential doublegrounded bipolar stage as core and tank; the latter is made up of an inductive and a capacitive part in parallel. No external devices are necessary. The capacitive part consists of a digital controlled switch cap tuning array and analog controlled varactor. The main reason to use a
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5108B-WiMax-2/06
combined analog and digital - hybrid - operating phase locked loop (Hybrid PLL) is to overcome tolerance, noise and integration problems in the VCO. Because of the course digital tuning, the analog tuning gain could be reduced so that the characteristic impedance of the loop filter increases and the charge pump current is reduced. That helps to integrate the whole active loop filter (APLL). Use of two (proportional and integral component) charge pumps and programming their currents permit changing of filter parameters. The phase interpolation divider (PDIV) is an alternate of a conventional modulus divider. It has the speed and power advantages of an asynchron divider and is programmable in a restricted range.
Calibration Support
Calibration of transceiver imbalances has to be performed by appendant BB/MAC processor. This processor generates corresponding control signals. The AT86RF535A contains additional analog calibration modules detecting for excellent calibration support: 1. LO signal leakage, 2. IQ signal imbalances in the TX Path, and 3. IQ signal imbalances in the RX Path. The control values will be given as analog control voltage.
SPI Interface
Serial peripheral interface (SPI) controls the transceiver. This 4-wire bus contains the ports SDE, SCL, SDI and SDO. The SPI has an 8-bit organization. Each transmission starts with a command byte with following structure:
Table 4.
MSB CMD
SPI Interface Structure
LSB ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
The command bit CMD is set to "1" for WRITE operation and "0" for READ operation. The transmission continues with the data bytes. The number of data bytes depends on the register. The MSB of each data byte is sent first.
Table 5.
MSB DATA7
For an 8 Bit Register
LSB DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
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AT86RF535A [Preliminary]
5108B-WiMax-2/06
AT86RF535A [Preliminary]
Table 6.
MSB DATA15 DATA7 DATA14 DATA6 DATA13 DATA5 DATA12 DATA4 DATA11 DATA3 DATA10 DATA2 DATA9 DATA1
For a 16 Bit Register
LSB DATA8 DATA0
Figure 2.
SPI Transmission for Multiple Bytes
SDE
SCL
SDI
X
CMD
ADR 6 ADR 5
ADR 4
ADR 3
ADR 2
ADR 1
ADR0
IN MSB OUT MSB
IN LSB OUT LSB
SDO
X
CMD
ADR 6
ADR 5
ADR 4
ADR 3
ADR 2
ADR 1
ADR 0
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5108B-WiMax-2/06
Pin Description & Package Drawing
Table 7.
PIN NIER NIET PRX PTX
Pin Description
PIN No. 1 2 3 4 DESCRIPTION Interface Enable RX Gain Control Low active, input enable of the serial RX gain control interface Interface Enable TX Level Control Low active, input enable of the serial TX level control interface Power Switch of Receive Path High active, digital CMOS input levels Power Switch Transmit Path High active, digital CMOS input levels RF Receive Input 1 Low noise amplifier input. The 50 matching is, in part, the bond/package inductance and an external component (tbd). RF Receive Input 2 Complementary signal to RFRX1 Ground Supply of Radio Frequency Receive Circuit Modules Voltage Supply of Radio Frequency Receive Circuit Modules RF Transmit Output 1 P1dB up to +10dBm @ 50 differential 3.5GHz. The 50 matching is, in part, the bond/package inductance and an external component (tbd). RF Transmit Output 2 Complementary signal to RFTX1 Voltage Supply of Power Amplifier Driving Module Voltage Supply of Radio Frequency Transmit Circuit Modules Digital Test Bus Input/Output Digital DTB input/output signal for testing purposes, connection and direction is configurable over SPI. Power On Reset Low active, open drain output with internal 10k pull up resistor SPI Data Digital Output SPI Enable Digital Input The rising edge of SCL and a low SDE indicate the start of a data transmission to the SPI slave SPI Data Digital Input Serial SPI data input stream is initiated with SDE and begins with an address byte. Input is MSB first. The MSB of the address byte is the R/W control bit. A number of data bytes follows after the address byte. The actual number of data bytes depends on the address. SPI Clock Digital Input At every rising edge, the SDI data is latched into the internal SPI register. SDO data change also on the rising edge. Voltage Supply of SPI Interface Pads Voltage Supply of Digital Circuit Modules Ground Supply SPI Interface Pads and of Digital Circuit Modules
RFRX1
5
RFRX2 VSSRFRX VDDRFRX RFTX1
6 7 8 9
RFTX2 VDDPA VDDRFTX2 DTB NRES SDO NSDE
10 11 12 13 14 15 16
SDI
17
SCL VDDSPI VDDDIG1 VSSDIG1
18 19 20 21
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AT86RF535A [Preliminary]
5108B-WiMax-2/06
AT86RF535A [Preliminary]
Table 7.
PIN VDDRFTX1 VDDBBTX BBTXQN BBTXQP BBTXIP BBTXIN EXCLE VDDCLK VSSCLK CLK VSSDIG3 VDDDIG3 VDDXTAL XTAL2 VSSXTAL XTAL1 ATB VDDCHP VSSCHP CHPO CVI VCMD
Pin Description (Continued)
PIN No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DESCRIPTION Voltage Supply of Radio Frequency Transmit Circuit Modules Voltage Supply of BB TX circuit modules Base Band Transmit Input Q Negative Base Band transmit input signal Quad Phase Base Band Transmit Input P Positive Complementary signal to BBTXQN Base Band Transmit Input I Positive Base band transmit input signal In Phase Base Band Transmit Input I Negative Complementary signal to BBTXIP External Clock Enable High active, digital CMOS input levels Voltage Supply of CMOS Clock I/O Modules Ground Supply of CMOS Clock I/O Modules 32/40MHz CMOS Clock digital I/O Direction depend on XTALE Ground Supply of Synthesizer Divider Modules and Digital Modules Voltage Supply of Synthesizer Divider Modules and Digital Modules Voltage Supply of Crystal Circuit Modules Crystal connection 32/40MHz Analog IO Ground Supply of Crystal Circuit Modules Crystal connection 32/40MHz Analog IO Analog Test Bus Analog IO Analog output/input signal for testing purposes, connection configurable over SPI Voltage Supply of Phase Frequency Detector and Charge Pump Modules Ground Supply of Phase Frequency Detector and Charge Pump Modules Charge Pump Current Output For external filter mode, configurable by SPI Control Voltage Input for external Loop Filter Configurable over SPI register Common Mode Voltage Bias Output RX Elements DC output voltage 1.0V, only active if PRX=High Base Band Receive Output I Negative In Phase output negative. The base band-processed signal is level voltage programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric Base Band Receive Output I Positive Complementary signal to BBRXIN
BBRXIN
44
BBRXIP
45
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5108B-WiMax-2/06
Table 7.
PIN BBRXQP
Pin Description (Continued)
PIN No. 46 DESCRIPTION Base Band Receive Output Q Positive Quad Phase output positive. The base band-processed signal is voltage level programmable to adapt to different base band ADCs. The capacitive load should be less than 10pF asymmetric. Base Band Receive Output Q Negative Complementary signal to BBRXQP Voltage Supply of BB Receive circuit modules Voltage Supply of BB Receive circuit modules Voltage Supply of Synthesizer modules VCO and APLF Ground Supply of Synthesizer modules VCO and APLF Voltage Supply of BB Interface Pads Ground Supply of BB Interface Pads and of Digital Circuit Modules Interface Data Data input of the serial gain, level and frequency control interface Interface Clock Clock input of the serial gain, level and frequency control interface Voltage Supply of Digital Circuit Modules
BBRXQN VSSBBRX VDDBBRX VDDVCO VSSVCO VDDBBIF VSSDIG2 IDA ICL VDDDIG2 Note:
47 48 49 50 51 52 53 54 55 56
Additional ground supplies are generated by down bonds to the exposed paddle.
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AT86RF535A [Preliminary]
5108B-WiMax-2/06
AT86RF535A [Preliminary]
Figure 3. Pinning Information
VDDBBRX
VSSBBRX
VDDDIG2
VSSDIG2 VDDBBIF
BBRXQN
VDDVCO
VSSVCO
BBRXQP
BBRXIN
PIN44
BBRXIP
PIN56
PIN55
PIN54
PIN53
PIN51
PIN49
PIN47
PIN45
PIN52
PIN50
PIN48
PIN46
PIN43
VCMD
ICL
IDA
NIER NIET PRX PTX RFRX1 RFRX2 VSSRFRX VDDRFRX RFTX1 RFTX2 VDDPA VDDRFTX2 DTB NRES
PIN1 AT86RF535 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14
PIN42 PIN41 PIN40 PIN39 PIN38 PIN37
CVI CHPO VSSCHP VDDCHP ATB XTAL1 VSSXTAL XTAL2 VDDXTAL VDDDIG3 VSSDIG3 CLK VSSCLK VDDCLK
QFN56
PIN36 PIN35 PIN34 PIN33 PIN32 PIN31 PIN30 PIN29
PIN23
PIN28
PIN22
PIN27
PIN21
PIN20
PIN19
PIN18
PIN17
PIN16
PIN26
PIN15
PIN25
PIN24
BBTXQP
VSSDIG1
BBTXQN
SDO
BBTXIP
VDDSPI
VDDDIG1
SCL
VDDRFTX1
VDDBBTX
BBTXIN
SDI
NSDE
EXCLE
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5108B-WiMax-2/06
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